Clear and Present Tensions in Microprocessor Design

Microprocessor performance can be improved by increasing either the clock frequency (GHz) or the instruction level parallelism (IPC) or both. There is a complex and adversarial relationship between increasing GHz and increasing IPC. This talk revisits the old “speed-demons vs. brainiacs” debate (in some sense the reincarnation of the “RISC vs. CISC” debate) and recasts it as the tension between performance and implementation efficiency. Hardware and software evolve at widely differing rates. Hardware designs evolve quickly to take advantage of each new technology generation. Legacy software tends to persist for decades. There is also a strong trend towards portable code. There is an increasing incompatibility between legacy/portable code and the latest/best execution cores. To achieve performance and efficiency, future microprocessor designs must effectively manage this tension between hardware and software Dr. John P. Shen is currently the director of the Microarchitecture Lab (uAL) in Intel's Microprocessor Research Labs (MRL). MRL-uAL's mission is to explore new innovative microarchitecture techniques in support of both IA32 and Itanium product groups. Prior to joining Intel in 2000, he was a Professor in the ECE Department at CMU where he directed the Carnegie Mellon Microarchitecture Research Team (CMuART). He received his degrees from Michigan (BS) and USC (MS, PhD) and had previously worked at Hughes and TRW. He is an IEEE Fellow and currently writing a textbook on “Fundamentals of Superscalar Microprocessor Design.” Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors (ICCD’01) 1063-6404/01 $10.00 © 2001 IEEE